Release: 2020.2
================

This release is validated on QDMA4.0 2020.2 based example design and
QDMA3.1 2019.2 patch based example design.

QDMA Windows driver is supported in poll mode by default

SUPPORTED FEATURES:
===================
2019.1 Features
---------------
- Support for AXI4 Memory Mapped(MM) and AXI4 Streaming(ST) Interfaces
- Supports only Physical Functions(PFs)
- 2048 queues Sets (512 queues for each PF)
	- 2048 H2C(host-to-card) Descriptor rings
	- 2048 C2H (card-to-host) Descriptor rings
	- 2048 Completion rings
- Interrupts
	- Up to 8 MSI-X vectors per Function
	- Interrupt Aggregation with single ring per PF
- Driver can be loaded in
	- Poll mode
	- direct interrupt mode
	- interrupt aggregation mode
- Queues are managed by synchronous/Asynchronous IO from single application.
- Driver configuration through qdma.inf file
- Zero Packet size Write/Read support for ST mode
- Descriptor bypass(8,16,32 descriptor sizes) support
- Descriptor Prefetch

2019.2 Features
---------------
- Support disabling overflow check in completion ring
- Support 64B descriptor format in bypass mode
- Support for Completion queue descriptors of 64 bytes size
- Legacy Interrupt Support
- Support HW Error reporting
- Support Completions in Streaming mode
- Support flexible BAR mapping for QDMA configuration register space
- Version for SW and HW
- ST H2C to C2H loopback support
- Enhancements to user application utilities

2020.1 Updates
---------------
- QDMA driver and libqdma as a separate project
- Configurable queue distribution between physical functions
- User application utility names changed as dma-ctl, dma-arw, dma-rw
- New set of commands added to dma-ctl application
- Support QDMA4.0 context and register changes
- Common driver to support QDMA3.1 and QDMA4.0 designs
- Updated and validated the example design with marker changes for QDMA4.0 and without marker changes for QDMA3.1
- Support multiple bus numbers on single card

2020.2 Updates
--------------
- Support larger MM & ST packet transfer support
- Added support for detailed register dump
- Added support for post processing HW error messages
- Added support for Debug mode and Internal only mode


KNOWN ISSUES:
=============
- Driver installation gives warning due to test signature.
- In interrupt mode, Sometimes completions are not received when C2H PIDX updates are held for 64 descriptors
- On QDMA4.0 2020.2 design, User logic fails to generate C2H streaming packets when multiple threads try
  to generate packets on multiple active queues.

DRIVER LIMITATIONS:
===================
- SRIOV is not supported
- Big endian systems are not supported
- Driver is not fully tuned to achieve maximum IP performance
- For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes.
