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usrp_basic.h

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00001 /* -*- c++ -*- */
00002 /*
00003  * Copyright 2003,2004,2008 Free Software Foundation, Inc.
00004  * 
00005  * This file is part of GNU Radio
00006  * 
00007  * GNU Radio is free software; you can redistribute it and/or modify
00008  * it under the terms of the GNU General Public License as published by
00009  * the Free Software Foundation; either version 3, or (at your option)
00010  * any later version.
00011  * 
00012  * GNU Radio is distributed in the hope that it will be useful,
00013  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00014  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015  * GNU General Public License for more details.
00016  * 
00017  * You should have received a copy of the GNU General Public License
00018  * along with GNU Radio; see the file COPYING.  If not, write to
00019  * the Free Software Foundation, Inc., 51 Franklin Street,
00020  * Boston, MA 02110-1301, USA.
00021  */
00022 
00023 /*
00024  * ----------------------------------------------------------------------
00025  * Mid level interface to the Universal Software Radio Peripheral (Rev 1)
00026  *
00027  * These classes implement the basic functionality for talking to the
00028  * USRP.  They try to be as independent of the signal processing code
00029  * in FPGA as possible.  They implement access to the low level
00030  * peripherals on the board, provide a common way for reading and
00031  * writing registers in the FPGA, and provide the high speed interface
00032  * to streaming data across the USB.
00033  *
00034  * It is expected that subclasses will be derived that provide
00035  * access to the functionality to a particular FPGA configuration.
00036  * ----------------------------------------------------------------------
00037  */
00038 
00039 #ifndef INCLUDED_USRP_BASIC_H
00040 #define INCLUDED_USRP_BASIC_H
00041 
00042 #include <db_base.h>
00043 #include <usrp_slots.h>
00044 #include <string>
00045 #include <vector>
00046 #include <boost/utility.hpp>
00047 #include <usrp_subdev_spec.h>
00048 
00049 struct usb_dev_handle;
00050 class  fusb_devhandle;
00051 class  fusb_ephandle;
00052 
00053 enum txrx_t {
00054   C_RX = 0,
00055   C_TX = 1
00056 };
00057 
00062 class usrp_basic : boost::noncopyable
00063 {
00064 protected:
00065   void shutdown_daughterboards();
00066 
00067 protected:
00068   struct usb_dev_handle *d_udh;
00069   int                    d_usb_data_rate;       // bytes/sec
00070   int                    d_bytes_per_poll;      // how often to poll for overruns
00071   bool                   d_verbose;
00072   long                   d_fpga_master_clock_freq;
00073 
00074   static const int       MAX_REGS = 128;
00075   unsigned int           d_fpga_shadows[MAX_REGS];
00076 
00077   int                    d_dbid[2];             // daughterboard ID's (side A, side B)
00078 
00087   std::vector< std::vector<db_base_sptr> > d_db;
00088 
00090   void init_db(usrp_basic_sptr u);
00091 
00092 
00093   usrp_basic (int which_board,
00094               struct usb_dev_handle *open_interface (struct usb_device *dev),
00095               const std::string fpga_filename = "",
00096               const std::string firmware_filename = "");
00097 
00107   void set_usb_data_rate (int usb_data_rate);
00108   
00119   bool _write_aux_dac (int slot, int which_dac, int value);
00120 
00129   bool _read_aux_adc (int slot, int which_adc, int *value);
00130 
00138   int _read_aux_adc (int slot, int which_adc);
00139 
00140 
00141 public:
00142   virtual ~usrp_basic ();
00143 
00144 
00152   std::vector<std::vector<db_base_sptr> > db() const { return d_db; }
00153 
00163   std::vector<db_base_sptr> db(int which_side);
00164  
00168   bool is_valid(const usrp_subdev_spec &ss);
00169 
00176   db_base_sptr selected_subdev(const usrp_subdev_spec &ss);
00177 
00181   long fpga_master_clock_freq () const { return d_fpga_master_clock_freq; }
00182 
00190   void set_fpga_master_clock_freq (long master_clock) { d_fpga_master_clock_freq = master_clock; }
00191 
00195   int usb_data_rate () const { return d_usb_data_rate; }
00196 
00197   void set_verbose (bool on) { d_verbose = on; }
00198 
00200   static const int READ_FAILED = -99999;
00201 
00209   bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
00210 
00218   std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
00219 
00227   bool write_i2c (int i2c_addr, const std::string buf);
00228 
00236   std::string read_i2c (int i2c_addr, int len);
00237 
00243   bool set_adc_offset (int which_adc, int offset);
00244 
00252   bool set_dac_offset (int which_dac, int offset, int offset_pin);
00253 
00260   bool set_adc_buffer_bypass (int which_adc, bool bypass);
00261 
00282   bool set_dc_offset_cl_enable(int bits, int mask);
00283 
00289   std::string serial_number();
00290 
00300   virtual int daughterboard_id (int which_side) const = 0;
00301 
00306   bool write_atr_tx_delay(int value);
00307 
00312   bool write_atr_rx_delay(int value);
00313 
00314 
00315   // ================================================================
00316   // Routines to access and control daughterboard specific i/o
00317   //
00318   // Those with a common_ prefix access either the Tx or Rx side depending
00319   // on the txrx parameter.  Those without the common_ prefix are virtual
00320   // and are overriden in usrp_basic_rx and usrp_basic_tx to access the
00321   // the Rx or Tx sides automatically.  We provide the common_ versions
00322   // for those daughterboards such as the WBX and XCVR2450 that share
00323   // h/w resources (such as the LO) between the Tx and Rx sides.
00324 
00325   // ----------------------------------------------------------------
00326   // BEGIN common_  daughterboard control functions
00327 
00341   bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db);
00342 
00349   double common_pga(txrx_t txrx, int which_amp) const;
00350 
00355   double common_pga_min(txrx_t txrx) const;
00356 
00361   double common_pga_max(txrx_t txrx) const;
00362 
00367   double common_pga_db_per_step(txrx_t txrx) const;
00368 
00385   bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask);
00386 
00395   bool common_write_io(txrx_t txrx, int which_side, int value, int mask);
00396 
00404   bool common_read_io(txrx_t txrx, int which_side, int *value);
00405 
00413   int common_read_io(txrx_t txrx, int which_side);
00414 
00436   bool common_write_refclk(txrx_t txrx, int which_side, int value);
00437 
00466   bool common_write_atr_mask(txrx_t txrx, int which_side, int value);
00467   bool common_write_atr_txval(txrx_t txrx, int which_side, int value);
00468   bool common_write_atr_rxval(txrx_t txrx, int which_side, int value);
00469 
00481   bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value);
00482 
00492   bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value);
00493 
00502   int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc);
00503 
00504   // END common_ daughterboard control functions
00505   // ----------------------------------------------------------------
00506   // BEGIN virtual daughterboard control functions
00507 
00520   virtual bool set_pga (int which_amp, double gain_in_db) = 0;
00521 
00527   virtual double pga (int which_amp) const = 0;
00528 
00532   virtual double pga_min () const = 0;
00533 
00537   virtual double pga_max () const = 0;
00538 
00542   virtual double pga_db_per_step () const = 0;
00543 
00559   virtual bool _write_oe (int which_side, int value, int mask) = 0;
00560 
00568   virtual bool write_io (int which_side, int value, int mask) = 0;
00569 
00576   virtual bool read_io (int which_side, int *value) = 0;
00577 
00584   virtual int read_io (int which_side) = 0;
00585 
00606   virtual bool write_refclk(int which_side, int value) = 0;
00607 
00608   virtual bool write_atr_mask(int which_side, int value) = 0;
00609   virtual bool write_atr_txval(int which_side, int value) = 0;
00610   virtual bool write_atr_rxval(int which_side, int value) = 0;
00611 
00622   virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0;
00623 
00632   virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0;
00633 
00641   virtual int read_aux_adc (int which_side, int which_adc) = 0;
00642 
00646   virtual int block_size() const = 0;
00647 
00651   virtual long converter_rate() const = 0;
00652 
00653   // END virtual daughterboard control functions
00654 
00655   // ----------------------------------------------------------------
00656   // Low level implementation routines.
00657   // You probably shouldn't be using these...
00658   //
00659 
00660   bool _set_led (int which_led, bool on);
00661 
00668   bool _write_fpga_reg (int regno, int value);  //< 7-bit regno, 32-bit value
00669 
00676   bool _read_fpga_reg (int regno, int *value);  //< 7-bit regno, 32-bit value
00677 
00683   int  _read_fpga_reg (int regno);
00684 
00693   bool _write_fpga_reg_masked (int regno, int value, int mask);
00694 
00702   bool _write_9862 (int which_codec, int regno, unsigned char value);
00703 
00711   bool _read_9862 (int which_codec, int regno, unsigned char *value) const;
00712 
00719   int  _read_9862 (int which_codec, int regno) const;
00720 
00734   bool _write_spi (int optional_header, int enables, int format, std::string buf);
00735 
00736   /*
00737    * \brief Read data from SPI bus peripheral.
00738    *
00739    * \param optional_header     0,1 or 2 bytes to write before buf.
00740    * \param enables             bitmask of peripheral to read. See usrp_spi_defs.h
00741    * \param format              transaction format.  See usrp_spi_defs.h SPI_FMT_*
00742    * \param len                 number of bytes to read.  Must be in [0,64].
00743    * \returns the data read if sucessful, else a zero length string.
00744    *
00745    * Reads are limited to a maximum of 64 bytes.
00746    *
00747    * If \p format specifies that optional_header bytes are present, they
00748    * are written to the peripheral first.  Then \p len bytes are read from
00749    * the peripheral and returned.
00750    */
00751   std::string _read_spi (int optional_header, int enables, int format, int len);
00752 
00757   bool start ();
00758 
00763   bool stop ();
00764 };
00765 
00766 
00770 class usrp_basic_rx : public usrp_basic 
00771 {
00772 private:
00773   fusb_devhandle        *d_devhandle;
00774   fusb_ephandle         *d_ephandle;
00775   int                    d_bytes_seen;          // how many bytes we've seen
00776   bool                   d_first_read;
00777   bool                   d_rx_enable;
00778 
00779 protected:
00788   usrp_basic_rx (int which_board,
00789                  int fusb_block_size=0,
00790                  int fusb_nblocks=0,
00791                  const std::string fpga_filename = "",
00792                  const std::string firmware_filename = ""
00793                  );  // throws if trouble
00794 
00795   bool set_rx_enable (bool on);
00796   bool rx_enable () const { return d_rx_enable; }
00797 
00798   bool disable_rx ();           // conditional disable, return prev state
00799   void restore_rx (bool on);    // conditional set
00800 
00801   void probe_rx_slots (bool verbose);
00802 
00803 public:
00804   ~usrp_basic_rx ();
00805 
00816   static usrp_basic_rx *make (int which_board,
00817                               int fusb_block_size=0,
00818                               int fusb_nblocks=0,
00819                               const std::string fpga_filename = "",
00820                               const std::string firmware_filename = ""
00821                               );
00822 
00832   bool set_fpga_rx_sample_rate_divisor (unsigned int div);
00833 
00842   int read (void *buf, int len, bool *overrun);
00843 
00844 
00846   virtual long converter_rate() const { return fpga_master_clock_freq(); } // 64M
00847   long adc_rate() const { return converter_rate(); }
00848   int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
00849 
00850   bool set_pga (int which_amp, double gain_in_db);
00851   double pga (int which_amp) const;
00852   double pga_min () const;
00853   double pga_max () const;
00854   double pga_db_per_step () const;
00855 
00856   bool _write_oe (int which_side, int value, int mask);
00857   bool write_io (int which_side, int value, int mask);
00858   bool read_io (int which_side, int *value);
00859   int read_io (int which_side);
00860   bool write_refclk(int which_side, int value);
00861   bool write_atr_mask(int which_side, int value);
00862   bool write_atr_txval(int which_side, int value);
00863   bool write_atr_rxval(int which_side, int value);
00864 
00865   bool write_aux_dac (int which_side, int which_dac, int value);
00866   bool read_aux_adc (int which_side, int which_adc, int *value);
00867   int  read_aux_adc (int which_side, int which_adc);
00868 
00869   int block_size() const;
00870 
00871   // called in base class to derived class order
00872   bool start ();
00873   bool stop ();
00874 };
00875 
00876 
00880 class usrp_basic_tx : public usrp_basic 
00881 {
00882 private:
00883   fusb_devhandle        *d_devhandle;
00884   fusb_ephandle         *d_ephandle;
00885   int                    d_bytes_seen;          // how many bytes we've seen
00886   bool                   d_first_write;
00887   bool                   d_tx_enable;
00888 
00889  protected:
00898   usrp_basic_tx (int which_board,
00899                  int fusb_block_size=0,
00900                  int fusb_nblocks=0,
00901                  const std::string fpga_filename = "",
00902                  const std::string firmware_filename = ""
00903                  );             // throws if trouble
00904 
00905   bool set_tx_enable (bool on);
00906   bool tx_enable () const { return d_tx_enable; }
00907 
00908   bool disable_tx ();           // conditional disable, return prev state
00909   void restore_tx (bool on);    // conditional set
00910 
00911   void probe_tx_slots (bool verbose);
00912 
00913 public:
00914 
00915   ~usrp_basic_tx ();
00916 
00927   static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int fusb_nblocks=0,
00928                               const std::string fpga_filename = "",
00929                               const std::string firmware_filename = ""
00930                               );
00931 
00941   bool set_fpga_tx_sample_rate_divisor (unsigned int div);
00942 
00952   int write (const void *buf, int len, bool *underrun);
00953 
00954   /*
00955    * Block until all outstanding writes have completed.
00956    * This is typically used to assist with benchmarking
00957    */
00958   void wait_for_completion ();
00959 
00961   virtual long converter_rate() const { return fpga_master_clock_freq () * 2; } // 128M
00962   long dac_rate() const { return converter_rate(); }
00963   int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
00964 
00965   bool set_pga (int which_amp, double gain_in_db);
00966   double pga (int which_amp) const;
00967   double pga_min () const;
00968   double pga_max () const;
00969   double pga_db_per_step () const;
00970 
00971   bool _write_oe (int which_side, int value, int mask);
00972   bool write_io (int which_side, int value, int mask);
00973   bool read_io (int which_side, int *value);
00974   int read_io (int which_side);
00975   bool write_refclk(int which_side, int value);
00976   bool write_atr_mask(int which_side, int value);
00977   bool write_atr_txval(int which_side, int value);
00978   bool write_atr_rxval(int which_side, int value);
00979 
00980   bool write_aux_dac (int which_side, int which_dac, int value);
00981   bool read_aux_adc (int which_side, int which_adc, int *value);
00982   int read_aux_adc (int which_side, int which_adc);
00983 
00984   int block_size() const;
00985 
00986   // called in base class to derived class order
00987   bool start ();
00988   bool stop ();
00989 };
00990 
00991 #endif

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